MMA6556KW【PDF 24/53 页】IC ACCELEROMETER X AXIS 16QFN

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3.7

ΣΔ Converter

A sigma delta converter provides the interface between the transducer and the DSP. The output of the ΣΔ converter is a data

stream at a nominal frequency of 1 MHz.

g-CELL

C TOP

C BOT

α 1 =

V X

C INT1

FIRST

INTEGRATOR

z -1

1 - z -1

α 2

SECOND

INTEGRATOR

z -1

1 - z -1

1-BIT

QUANTIZER

ΣΔ _OUT

ADC

Δ C = C TOP - C BOT

β 1

β 2

V = Δ C x V X / C INT1

V = ± 2 × V REF

Figure 11. ΣΔ Converter Block Diagram

DAC

3.8

Digital Signal Processing Block

A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating

the signal processing flow is shown in Figure 12 .

Arm/PCM Output

Section 3.8.9

I

To ARM

ΣΔ _OUT

A

SINC Filter

B

Low Pass Filter

C Compensation D

Interpolation

E

Offset Cancellation

F

Offset Cancellation

G

Section 3.8.10

To SPI

Section 3.8.2

Section 3.8.3

Section 3.8.6

Section 3.8.7

Section 3.8.4

Output Scaling

Table 23. Signal Chain Characteristics

Figure 12. Signal Chain Diagram

Raw Output

Scaling

H

To SPI

A

B

Description

SD

SINC Filter

Sample

Time ( μ s)

1

8

Data Width

Bits

1

14

Over Range

Bits

Effective

Bits

1

13

Rounding

Resolution Bits

Typical Block

Latency

3.2 μ s

11.2 μ s

Reference

Section 3.7

Section 3.8.2

C

D

E

F

Low Pass Filter

Compensation

Interpolation

Offset

Cancellation

8/16

8/16

4/8

256

20

20

20

20

4

4

4

4

12

12

12

12

4

4

4

4

Reference

Section 3.8.3

7.875 μ s

t s / 2

N/A

Section 3.8.3

Section 3.8.6

Section 3.8.8

Section 3.8.4

GH

I

SPI Output

PCM Output

4/8

4/8

—

—

—

—

12

9

—

—

t s / 2

Section 3.8.11

MMA655x

Sensor

24

Freescale Semiconductor, Inc.

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